Acceleration of Algorithms in
Reconfigurable Logic

Washington University in St. Louis
Fall 2024

Welcome! This is a graduate level CSE course that introduces the design of hardware accelerators for a specific application or class of applications. In this class, we will use Field Programmable Gate Arrays (FPGAs) as the medium for our hardware designs, and we will use high-level synthesis (HLS) – in contrast to low-level RTL – to author the designs. The goals of the class are to

• take applications of interest from algorithm to hardware design
• develop intuition for performant hardware architectures designed using HLS
• learn the fundamentals of the state of the art (SOTA) tooling for HLS